1. Field of the Invention
The present invention relates to methods of forming an electrode for an integrated circuit device.
2. Description of the Related Art
A transistor of integrated circuit device may include a gate electrode formed on an active region of a substrate, a gate insulating layer interposed between the gate electrode and the substrate, and at least one source/drain regions formed on the active region positioned at both sides of the gate electrode. A metal oxide semiconductor field effect transistor (MOSFET) may be employed in integrated circuit devices. The MOSFET may include a gate insulating layer formed on a substrate and a gate electrode formed on the gate insulating layer. A MOS type highly-integrated integrated circuit device may include a complement-MOS (C-MOS) type device that has both an N-MOS transistor and a P-MOS transistor.
The C-MOS type integrated circuit device may include a single kind of a conductive material as gate electrodes of the N-MOS transistor and the P-MOS transistor to simplify processes for manufacturing the C-MOS type integrated circuit device. The conductive material used as gate electrodes may include N type poly crystalline silicon. A silicon oxide layer including a thermal oxide layer may be used as a gate insulating layer. The gate electrode may include a doped polysilicon layer.
As semiconductor devices provide higher operating speeds, a thickness of the gate insulating layer may be reduced. When the thickness of the gate insulating layer is reduced to less than a critical thickness, a leakage current may occur thereby degrading characteristics of the semiconductor device. Recently, thickness of layers used as the gate insulating have approached this critical thickness. Thus, further reduction in thickness of silicon oxide layers used as gate insulating layers may be limited. Therefore, use of high-k dielectrics as gate insulating layers have been studied.
High-k dielectrics may provide improved characteristics with respect to reducing leakage currents even when an equivalent oxide thickness (EOT) is less than a critical thickness of a silicon oxide layer. The EOT of a high-k dielectrics layer means the thickness of a silicon oxide layer that would provide the same capacitance. Thus, use of a high-k dielectrics can provide a capacitance equivalent to that provided using a physically thinner silicon oxide layer while providing improved leakage current characteristics.
On the other hand, when a high-k dielectric is used as a gate insulating layer, the high-k dielectric may react with n-type polycrystalline used as the gate electrode to form a silicon oxide layer. As a result, the silicon oxide layer formed through the reaction may increase a total EOT of the gate insulating. In addition, a work function of the materials of the gate electrode may have an effect on electrical characteristics of the transistor.
FIGS. 1A to 1C are cross sectional views illustrating conventional art views depicting methods for forming a dual gate electrode. FIG. 1A illustrates an isolation layer 2 formed on a substrate 1. Impurities are illustrated doped into the substrate 1 to form a P type active region 3 and an N type active region 4. An N-MOS gate insulating layer 5 may then formed on the substrate 1. A P-MOS gate electrode layer 6 can then be formed on the N-MOS gate insulating layer 5 and the isolation layer 2.
FIG. 1B illustrates that the N-MOS gate electrode layer 6 and the N-MOS gate insulating layer 5 are etched to form an N-MOS gate electrode 6a disposed on the P type active region 3. A P-MOS gate insulating layer 7 is formed on the N-MOS gate electrode 6a and the substrate 1. A P-MOS gate electrode layer 8 is formed on the N-MOS gate electrode 6a and the isolation layer 2. Here, the work function of the P-MOS gate electrode 8 is greater than that of the N-MOS gate electrode 6a. 
FIG. 1C depicts that the P-MOS gate electrode layer and the P-MOS gate insulating layer are etched to form a P-MOS gate electrode 8a disposed on the N type active region 4. It is possible for the N-MOS gate electrode 6a to be damaged during the etching process of the P-MOS gate electrode 8 and the P-MOS gate insulating layer 7 to deteriorate an N-MOS transistor having the N-MOS gate electrode 6a during this process. Furthermore, the method for manufacturing the N-MOS gate electrode 6a and the P-MOS gate electrode 8a using a damascene process may cause additional damage to the electrodes.
An electrode of an integrated circuit device may include an electrode for a capacitor. A dynamic random access memory (DRAM) device may include a single access transistor and a single storage capacitor. The size of the capacitor can be reduced to increase the integration degree of a memory device.
The methods for improving capacitance may include methods for forming a dielectric layer using a high dielectric constant, a method for increasing the effective area of a capacitor or a method for reducing the thickness of a dielectric layer. Metal oxide material having a high dielectric constant, such as tantalum oxide (Ta2O5), titanium oxide (TiO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), barium titanium oxide (BaTiO3) or strontium titanium oxide (SrTiO3), may be used as the dielectric layer. U.S. Pat. No. 5,316,982, issued to Taniguchi illustrates a capacitor having a dielectric layer that includes metal oxide material. When the dielectric layer is formed using metal oxide material of the '982 patent, the metal oxide material may be readily reacted with an electrode layer of a capacitor. Oxygen contained in a metal oxide material may be readily reacted with silicon and may cause the deterioration of the characteristics of the capacitor. This, in turn, may result in a reduction in the reliability of an integrated circuit.
Materials used for an electrode that may be matched with the metal oxide material used for a dielectric layer may assist in reducing deterioration of the characteristics of the capacitor. U.S. Pat. No. 6,204,204 issued to Paranjpe et al., U.S. Pat. No. 6,153,519 issued to Jain et al., and U.S. Pat. No. 5,668,054 issued to Sun et al., illustrate method for forming a tantalum nitride layer as a thin metal layer. In a method disclosed in the U.S. Pat. No. 5,668,054, a tantalum nitride layer is formed through a chemical vapor deposition (CVD) process using terbutylimido-tris-diethylamino-tantalum ((Net2)3Ta=NtBu) (TBTDET) as a reactant. The CVD process is performed at a temperature of above about 600° C. When the CVD process is performed at a temperature of about 500° C., the tantalum nitride layer has a specific resistance of above about 10,000 Ωcm.
Other processes may be used to deposit the tantalum nitride layer. U.S. Pat. No. 6,203,613 issued to Gates et al. shows methods for forming tantalum nitride layer using an atomic layer deposition (ALD) process.
U.S. Pat. No. 6,357,901 issued to Cha et al. discloses method for forming a transistor of an integrated circuit device. In the '901 patent, an insulating layer is formed on a substrate defined N-MOS region and P-MOS region thereon. Atantalum layer or a tantalum nitride layer having a work function of about 4.0 eV to about 4.4 eV is formed on the gate insulating layer positioned on the N-MOS region. A tantalum layer or a tantalum nitride layer having a work function of about 4.8 eV to about 5.2 eV is formed on the gate insulating layer positioned on the P-MOS region. A metal layer having a low resistance such as tungsten is formed on the tantalum layers or the tantalum nitride layers. Here, TaCl, Ta(OCH), tetrakis dimethylamido titanium (TDMAT) or tetrakis diethylamino titanium (TDEAT) is used as a precursor of tantalum.
U.S. Pat. No. 6,504,214 issued to Yu et al. discloses a method for manufacturing a MOSFET that includes a dielectric layer having a high dielectric constant. In the '214 patent, a gate insulating layer having a high dielectric constant is formed on a substrate having a buffer surface. A gate electrode including tungsten, tantalum, titanium nitride or tantalum nitride is formed on the gate insulating layer. A gate electrode contact including metal silicide or metal is formed on the gate electrode.
U.S. Pat. No. 6,492,217 issued to Bai et al. illustrates a method for forming a gate electrode. In the '217 patent, a gate dielectric layer is formed on a substrate. A barrier layer including titanium nitride, titanium silicon nitride or tantalum nitride is formed on the gate dielectric layer. A gate electrode is formed on the barrier layer.
U.S. Pat. No. 6,168,991 issued to Choi et al. depicts method for manufacturing a capacitor of a DRAM cell. In the '991 patent, a first electrode layer including tantalum, tantalum nitride or a multi-layer thereof is formed on a substrate. The first electrode layer serves as a first electrode and a barrier layer. A dielectric layer having a high dielectric constant is formed on the first electrode layer. A second electrode layer having a material substantially identical to that of the first electrode layer is formed on the dielectric layer.
Ritala et al. in “Controlled Growth of TaN, Ta3N5 and TaOxNy Thin Films by Atomic Layer Deposition” illustrate the deposition of a thin tantalum nitride layer by an ALD method using TaCl5 source. Tsai et al. in “Metal Organic Chemical Vapor Deposition of Tantalum Nitride by Terbutylimidotris (Diethylamido) Tantalum for advanced metallization” illustrate a CVD method using a TBTDET source.
Japanese Patent Laid Open Publication No. 2002-193981 illustrates a method for fabricating Ta(NC(Ch3)2C2H5)(N(CH3)2)3) (TAIMATA) and a metal organic chemical vapor deposition (MOCVD) method using a precursor solution including the same. According to the methods disclosed, 1 mole of TaCl5, 4 moles of LiNMe2 and 1 mole of LiNHtAm are reacted with each other in an organic solution at a room temperature to form a compound. The compound is filtered. The organic solution is removed from the filtered compound to form Ta(NC(Ch3)2C2H5)(N(CH3)2)3). Ta(NC(Ch3)2C2H5)(N(CH3)2)3) is dissolved in a organic solution. Dissolved Ta(NC(Ch3)2C2H5)(N(CH3)2)3) is deposited on a substrate disposed in a CVD chamber to form a tantalum nitride layer.
The Japanese Patent Laid Open Publication discloses that the tantalum nitride layer is formed using only Ta(NC(Ch3)2C2H5)(N(CH3)2)3). Korean Patent Laid Open Publication No. 2003-9093 discloses a method for forming an atomic layer and a thin film using an organic metal precursor or a tantalum halide precursor. According to the disclosed method, a gaseous reactant is introduced into a chamber in which a substrate is disposed. The gaseous reactant is deposited on the substrate by atomic layer units.